philips semiconductors product specification trenchmos ? transistor BUK9606-55A logic level fet general description quick reference data n-channel enhancement mode logic symbol parameter max. unit level field-effect power transistor in a plastic envelope suitable for surface v ds drain-source voltage 55 v mounting. using ' trench ' technology i d drain current (dc) 75 a the device features very low on-state p tot total power dissipation 230 w resistance. it is intended for use in t j junction temperature 175 ?c automotive and general purpose r ds(on) drain-source on-state switching applications. resistance v gs = 5 v 6.3 m w v gs = 10 v 5.8 m w pinning - sot404 pin configuration symbol pin description 1 gate 2 drain (no connection possible) 3 source mb drain limiting values limiting values in accordance with the absolute maximum system (iec 134) symbol parameter conditions min. max. unit v ds drain-source voltage - - 55 v v dgr drain-gate voltage r gs = 20 k w -55v v gs gate-source voltage - - 10 v v gsm non-repetitive gate-source voltage t p 50 m s - 15 v i d drain current (dc) t mb = 25 ?c - 75 a i d drain current (dc) t mb = 100 ?c - 75 a i dm drain current (pulse peak value) t mb = 25 ?c - 240 a p tot total power dissipation t mb = 25 ?c - 230 w t stg , t j storage & operating temperature - - 55 175 ?c thermal resistances symbol parameter conditions typ. max. unit r th j-mb thermal resistance junction to - - 0.65 k/w mounting base r th j-a thermal resistance junction to minimum footprint, fr4 50 - k/w ambient board d g s 13 mb 2 january 1999 1 rev 1.000
philips semiconductors product specification trenchmos ? transistor BUK9606-55A logic level fet static characteristics t j = 25?c unless otherwise specified symbol parameter conditions min. typ. max. unit v (br)dss drain-source breakdown v gs = 0 v; i d = 0.25 ma; 55 - - v voltage t j = -55?c 50 - - v v gs(to) gate threshold voltage v ds = v gs ; i d = 1 ma 1 1.5 2.0 v t j = 175?c 0.5 - - v t j = -55?c - - 2.3 v i dss zero gate voltage drain current v ds = 55 v; v gs = 0 v; - 0.05 10 m a t j = 175?c - - 500 m a i gss gate source leakage current v gs = 10 v; v ds = 0 v - 2 100 na r ds(on) drain-source on-state v gs = 5 v; i d = 25 a - 5.3 6.3 m w resistance t j = 175?c - - 13.2 m w v gs = 10 v; i d = 25 a - 4.8 5.8 m w v gs = 4.5 v; i d = 25 a - - 6.7 m w dynamic characteristics t mb = 25?c unless otherwise specified symbol parameter conditions min. typ. max. unit c iss input capacitance v gs = 0 v; v ds = 25 v; f = 1 mhz - 6500 8600 pf c oss output capacitance - 1000 1200 pf c rss feedback capacitance - 650 850 pf t d on turn-on delay time v dd = 30 v; r load =1.2 w ; - 45 65 ns t r turn-on rise time v gs = 5 v; r g = 10 w - 180 270 ns t d off turn-off delay time - 420 590 ns t f turn-off fall time - 235 330 ns l d internal drain inductance measured from upper edge of drain - 2.5 - nh tab to centre of die l s internal source inductance measured from source lead - 7.5 - nh soldering point to source bond pad reverse diode limiting values and characteristics t j = 25?c unless otherwise specified symbol parameter conditions min. typ. max. unit i dr continuous reverse drain - - 75 a current i drm pulsed reverse drain current - - 240 a v sd diode forward voltage i f = 25 a; v gs = 0 v - 0.85 1.2 v i f = 75 a; v gs = 0 v - 1.1 - v t rr reverse recovery time i f = 75 a; -di f /dt = 100 a/ m s; - 80 - ns q rr reverse recovery charge v gs = -10 v; v r = 30 v - 0.2 - m c avalanche limiting value symbol parameter conditions min. typ. max. unit w dss drain-source non-repetitive i d = 75 a; v dd 25 v; - - 500 mj unclamped inductive turn-off v gs = 5 v; r gs = 50 w ; t mb = 25 ?c energy january 1999 2 rev 1.000
philips semiconductors product specification trenchmos ? transistor BUK9606-55A logic level fet fig.1. normalised power dissipation. pd% = 100 p d /p d 25 ?c = f(t mb ) fig.2. normalised continuous drain current. id% = 100 i d /i d 25 ?c = f(t mb ); conditions: v gs 3 5 v fig.3. safe operating area. t mb = 25 ?c i d & i dm = f(v ds ); i dm single pulse; parameter t p fig.4. transient thermal impedance. z th j-mb = f(t); parameter d = t p /t fig.5. typical output characteristics, t j = 25 ?c . i d = f(v ds ); parameter v gs fig.6. typical on-state resistance, t j = 25 ?c . r ds(on) = f(i d ); parameter v gs 0 20 40 60 80 100 120 140 160 180 tmb / c pd% normalised power derating 120 110 100 90 80 70 60 50 40 30 20 10 0 0.00001 0.001 0.1 10 0.001 0.01 0.1 1 d = t p t p t t p t d zth / (k/w) t/s d = 0.5 0.2 0.1 0.05 0.02 0 0246810 0 100 200 300 400 id/a vds/d vgs\v = 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 6.0 7.0 10.0 0 20 40 60 80 100 120 140 160 180 tmb / c id% normalised current derating 120 110 100 90 80 70 60 50 40 30 20 10 0 0 20406080100 5 5.5 6 6.5 7 7.5 8 8.5 rds(on)/mohm vgs/v = id/a 3.0 3.2 3.4 3.6 4.0 5.0 1 10 100 1 10 100 1000 id/a vds/v rds(on) = vds/id dc tp = 100ms 10ms 1ms 100us 10us january 1999 3 rev 1.000
philips semiconductors product specification trenchmos ? transistor BUK9606-55A logic level fet fig.7. typical on-state resistance, t j = 25 ?c . r ds(on) = f(v gs ); conditions: i d = 25 a; fig.8. typical transfer characteristics. i d = f(v gs ) ; conditions: v ds = 25 v; parameter t j fig.9. typical transconductance, t j = 25 ?c . g fs = f(i d ); conditions: v ds = 25 v fig.10. normalised drain-source on-state resistance. a = r ds(on) /r ds(on)25 ?c = f(t j ); i d = 25 a; v gs = 5 v fig.11. gate threshold voltage. v gs(to) = f(t j ); conditions: i d = 1 ma; v ds = v gs fig.12. sub-threshold drain current. i d = f(v gs) ; conditions: t j = 25 ?c; v ds = v gs 345678910 4 4.5 5 5.5 6 6.5 7 7.5 8 rds(on)/mohm vgs/v -100 -50 0 50 100 150 200 0.5 1 1.5 2 2.5 buk959-60 tmb / degc rds(on) normlised to 25degc 0 0.5 1 1.5 2 2.5 3 3.5 0 20 40 60 80 100 id/a vgs/v tj = 175 25 buk959-60 -100 -50 0 50 100 150 200 0 0.5 1 1.5 2 2.5 tj / c vgs(to) / v max. typ. min. 0 20406080100 0 50 100 150 gfs/s id/a 0 0.5 1 1.5 2 2.5 3 1e-05 1e-05 1e-04 1e-03 1e-02 1e-01 sub-threshold conduction 2% typ 98% january 1999 4 rev 1.000
philips semiconductors product specification trenchmos ? transistor BUK9606-55A logic level fet fig.13. typical capacitances, c iss , c oss , c rss . c = f(v ds ); conditions: v gs = 0 v; f = 1 mhz fig.14. typical turn-on gate-charge characteristics. v gs = f(q g ); conditions: i d = 50 a; parameter v ds fig.15. typical reverse diode current. i f = f(v sds ); conditions: v gs = 0 v; parameter t j fig.16. normalised avalanche energy rating. w dss % = f(t mb ); conditions: i d = 75 a fig.17. avalanche energy test circuit. fig.18. switching test circuit. 0.01 0.1 1 10 100 0 5 10 15 20 thousands pf vds/v ciss coss crss 20 40 60 80 100 120 140 160 180 tmb / c 120 110 100 90 80 70 60 50 40 30 20 10 0 wdss% 0 20 40 60 80 100 120 0 1 2 3 4 5 6 vgs/v qg/nc vds = 14v 44v l t.u.t. vdd rgs r 01 vds -id/100 + - shunt vgs 0 w dss = 0.5 li d 2 bv dss /( bv dss - v dd ) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 0 20 40 60 80 100 if/a vsds/v tj/c = 175 25 rd t.u.t. vdd rg vds + - vgs 0 january 1999 5 rev 1.000
philips semiconductors product specification trenchmos ? transistor BUK9606-55A logic level fet mechanical data fig.19. sot404 surface mounting package. centre pin connected to mounting base. notes 1. this product is supplied in anti-static packaging. the gate-source input must be protected against static discharge during transport or handling. 2. refer to smd footprint design and soldering guidelines, data handbook sc18. 3. epoxy meets ul94 v0 at 1/8". unit a references outline version european projection issue date iec jedec eiaj mm a 1 d 1 d e el p h d q c 2.54 2.60 2.20 15.4 14.8 2.9 2.1 9.65 8.65 1.6 1.2 10.3 9.7 4.5 4.1 1.40 1.27 0.85 0.60 0.64 0.46 b dimensions (mm are the original dimensions) sot404 97-06-16 0 2.5 5 mm scale plastic single-ended package (philips version of d2-pak); 2 leads sot404 e e e b d 1 h d d q l p c a 1 a january 1999 6 rev 1.000
philips semiconductors product specification trenchmos ? transistor BUK9606-55A logic level fet mounting instructions dimensions in mm fig.20. sot404 : soldering pattern for surface mounting . definitions data sheet status objective specification this data sheet contains target or goal specifications for product development. preliminary specification this data sheet contains preliminary data; supplementary data may be published later. product specification this data sheet contains final product specifications. limiting values limiting values are given in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of this specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the specification. philips electronics n.v. 1999 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. life support applications these products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. 17.5 11.5 9.0 5.08 3.8 2.0 january 1999 7 rev 1.000
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